1. Field of the Invention
The present invention relates generally to reducing hillock formation in the metal interconnection layer of a semiconductor device, and more particularly, to reducing lateral formation of hillocks therein to prevent occurrence of short circuits between metal interconnection disposed on a common layer of high density integrated circuit device.
2. Description of the Background Art
Multilayer interconnections are indispensable to semiconductor devices such as LSIs to improve packaging density. A conventional method of manufacturing a semiconductor device having multilayer interconnections will be described in the following, with reference to a bipolar IC. FIGS. 1A to 1H schematically show the steps of manufacturing a conventional bipolar IC.
(1) Referring to FIG. 1A, an N.sup.+ buried layer 2 is diffused on a main surface of a P type semiconductor substrate, for example, in order to reduce resistance between the collector and emitter of a transistor.
(2) Referring to FIG. 1B, an N layer 3 which will be the collector region of the transistor is formed on the main surface of the semiconductor substrate 1 by epitaxial growth.
(3) An IC comprises a number of transistors and diodes. In order to electrically separate these elements from each other, P+ layers 4 are diffused into the N layer 3, as shown in FIG. 1C. In the present manufacture of MOS integrated circuit, it is the usual practice to separate active areas of the semiconductor by use of isolation oxide which is also referred to as field oxide. Normally, the P.sup.+ layers 4 are maintained at a lowest potential in the circuit, and the elements are separated from each other by applying a reverse bias to the diodes formed between N layer 3 formed in the step (2).
(4) Referring to FIG. 1D, a p layer 5 which will be the base region of an npn transistor is formed in the N layer 3. The p layer 5 is also used as a resistance in of the circuits in the IC.
(5) Referring to FIG. 1E, an N.sup.+ layer 6 which will be the emitter region of the np transistor is formed in the p layer 5. At the same time, an N.sup.+ layer 7 which is necessary for taking out a collector electrode from the N layer 3 of the step (2) is formed.
(6) The steps of diffusion necessary for the operation of the transistor are completed thus far. Thereafter, as shown in FIG. 1F, an oxide film 8 is formed on the entire surface and contact holes are formed at prescribed portions of the oxide film 8 so as to connect respective regions with Al wirings.
(7) Referring to FIG. 1G, the elements are connected by the Al wirings 9.
(8) Thereafter, as shown in FIG. 1H, an interlayer insulating film 10 is formed on the entire surface, if necessary, and contact holes are formed on prescribed portions of the interlayer insulating film 10 to provide Al wirings 11 of the second layer, and the surface of the chip may be covered by a passivation film 12' to improve resistance against moisture.
The conventional method of manufacturing semiconductor devices comprises the above described steps. Problems occurred during manufacturing of conventional semiconductor devices having multilayer interconnection will be described in the following.
FIG. 2 is a schematic diagram of a semiconductor device having multilayer interconnection provided through the above described method. Referring to FIG. 2, wirings 11a and 11b are formed on a semiconductor substrate 1 with insulating films 10a and 10b interposed therebetween. Hillocks 40 extending in the upward and lateral directions are generated on the wiring 11a. The hillocks 40 are generated during thermal processing of the wiring 11a. If the hillocks 40 extend much in the upward direction, the hillocks 40 may possibly be in contact with the wiring 11b, causing short circuits between interconnections. The short circuits between interconnections caused by hillocks have been a serious problem which decreases reliability of the devices.
Therefore, in providing multilayer interconnections, the size of the hillocks 40 generated on the underlying wiring 11a must be reduced in size. The size of the hillocks 40 must be in the range of about 0.1 to 0.5 .mu.m in order to enable good interconnection.
How and why the hillocks are generated will be hereinafter described with reference to some articles. According to Japanese Patent Laying-Open No. 55-158649/1980, the vapor deposited aluminum is a granular material and is formed as an aggregation of large grains 50, as shown in FIG. 3A.
The aluminum which is an aggregation of grains 50 is heated, a force is applied by the heat in the direction shown by the arrows F as shown in FIG. 4, so that the grains 50 are brought into strong contact with each other. Consequently, hillocks are generated from the grains 50. The size of the hillocks is relative to the size of the grains 50. Namely, the larger becomes the size of the grain 50, the larger becomes the size of the generated hillocks. The size of the grain 50 is normally 1 to 2 .mu.m and hillocks of about 1 to 2 .mu.m are generated from the grains 50 of this size. As described above, in order to provide good interconnections, the size of the hillocks must be about 0.1 to 0.5 .mu.m.
Therefore, it is assumed that the size of the generated hillocks will be small when the grains are broken to small pieces as shown in FIG. 3B to reduce the size of the grains.
In view of the foregoing, the applicant of the present invention has proposed a method for breaking the grains into small pieces as shown in FIGS. 5A to 5C. The details of this process are disclosed in Japanese Patent Laying-Open No. 57-183053/1982, 57-183054/1982, 7-183055/1982 and 57-183056/1982. The conventional process of preventing generation of hillocks will be described in the following.
Referring to FIG. 5A, underlying wirings 13 are formed on the semiconductor substrate including devices, interlayer insulating film 14 is formed on the entire surface so as to cover the lower electrodes 13, and an upper layer Al wirings 15 are formed thereon.
Thereafter, referring to FIG. 5B, ion implantation 30 of Ar.sup.+, As.sup.+ P.sup.+, Sb.sup.+ or the like is carried out on the surface of the Al wirings 15 prior to the patterning of the same. By the ion implantation, the grains of aluminum having large size (see FIG. 3A) are broken into small grains as shown in FIG. 3B.
Thereafter, patterning of Al wirings 15 is carried out, as shown in FIG. 5C.
In this prior art, the grains of aluminum is broken to be reduced in size by ion implantation, so that the size of the hillocks extending upward becomes small. Consequently, short circuits between different layers of interconnections can be prevented.
Now, as the degree of integration of semiconductor devices have been increased, short circuits in the same interconnecting layer caused by contacts between hillocks extending in the lateral direction have become a new problem.
In the process shown in FIGS. 5A to 5C, ion implantation 30 is carried out vertically from above the Al wiring 15. Therefore, the grains existing on the upper surface of the Al wirings 15 are reduced in size, and accordingly, the hillocks extending upward are also reduced in size. However, the size of the hillocks extending in the lateral direction from the side walls of the Al wirings 15 could not be made small. Therefore, short circuits between Al wirings in the same layer could not be prevented by the above described process, so the problem remains unsolved, reducing the reliability.